1. Field of the Invention
The present invention relates to a cache memory, a processor for embedding the cache memory, and a cache control method of the cache memory.
2. Related Background Art
Operational speed of a CPU is going to become fast. Because it is impossible to operate a memory at speed higher than the CPU, a cache memory is generally provided in order to compensate a speed difference between the CPU and the memory.
A portion of data which has been stored or is to be stored in a main memory is stored in the cache memory in principle. Data in the cache memory maintains consistency with data in the main memory. Accordingly, data which has been stored in the cache memory and is not yet stored in the main memory has to be written back to the main memory, prior to update of the cache memory.
An ordinary main memory is composed of a plurality of ways which have a plurality of indexes and are arranged in parallel.
Although the cache memory is a memory faster than the main memory, a possibility in which cache miss occurs becomes very high, depending on a program executing by the CPU. Especially, in the case of continuously accessing different addresses more than the number of ways, cache miss may continuously occur. Therefore, it may take excess time or memory access.
As mentioned above, there is a likelihood that high performance of the cache memory is not effectively used depending on programs.